The present invention relates to a semiconductor device and a system. More particularly, the present invention relates to a technique usable effectively for an input circuit in each LSI/IC used in a system constituted of a plurality of LSIs/ICs, each having an input/output interface corresponding to a signal voltage different from others.
In an investigation of some well-known examples performed after the completion of the present invention, the present inventor et al have received a report of existence of official gazettes of (1) Japanese Unexamined Patent Publication No. Hei 5(1993)-266666 and (2) Japanese Unexamined Patent Publication No. 2001-251176 that are related to the present invention. The official gazette (1) discloses a semiconductor memory that can prevent transistors from destruction that might occur in the input circuit with use of an input amplitude limiting circuit disposed between an input terminal and the input circuit. The official gazette (2) discloses a level shifting circuit provided with a control circuit 30 for controlling a transfer gate 20. The transfer gate 20 is controlled not so as to receive a voltage over a predetermined withstand voltage of the gate oxide film even when the input voltage exceeds the predetermined withstand voltage.